As known to the art, the static RAM (SRAM) cell includes a complete CMOS type and an E/R type. The complete CMOS type SRAM Cell consists of six transistors including two PMOS transistors, two NMOS transistors, said PMOS and NMOS transistors forming a flip-flop circuit, and two pass-gate NMOS transistors serving to connect the flip-flop circuit to bit lines. On the other hand, the E/R type SRAM cell consists of four transistors and two resistors. These two resistors are formed of highly resistant polycrystalline silicon (polysilicon) and replace the two PMOS transistors included in the complete CMOS type SRAM cell.
The complete CMOS type SRAM cell can be operated with a high stability and with a small power consumption, but has a drawback that the cell area is large. The E/R type SRAM cell has an advantage of a decreased cell area because a polysilicon film of high resistance can be superposed on the NMOS transistor, with the result that the cell area is substantially equal to the sum of the areas required for the four NMOS transistors included in the cell. However, since resistors are used in place of the two PMOS transistors, the gain of the inverter is decreased, leading to a poor stability. In addition, when the NMOS transistor is turned on, current flows between Vcc and GND through the polysilicon layer of a high resistance, leading to an increased power consumption.
FIG. 9 shows a "butterfly" characteristics (the state in the reading step) of a complete CMOS type cell, and FIG. 10 shows that of an E/R type cell. It is clearly seen that the complete CMOS type cell is superior in stability to the E/R type cell. Further, FIG. 11 shows the current consumption with respect to the ambient temperature, in the stand-by mode or covering the case where each of the complete CMOS type cell and the E/R type cell is at rest. It is clearly seen that the power consumption of the complete CMOS type cell is smaller.
Recently, a semiconductor device is required to be operated with a low voltage (about 3.3 V) and with a small power consumption. It is difficult to meet these requirements in operating an E/R type cell with a high stability. Where the complete CMOS type cell comprising six transistors is allowed to be operated with a high stability and with a small power consumption, however, it is necessary to increase the cell area, resulting in failure to miniaturize the semiconductor device.
FIG. 13 is a plane view showing a conventional six transistor type SRAM cell, with FIG. 14 showing a cross section along line XIV--XIV shown in FIG. 13. Further, FIG. 15 schematically shows an array of SRAM cells shown in FIG. 13. As shown in these drawings, a P-well 32, an N-well 33, a P-channel stopper layer 34, a field oxide film 35, etc. are formed on the surface of an N-type Si substrate 31. An NMOS transistor Tr1 comprising an n.sup.+ -type source region 36, an n.sup.+ -type drain region 37 and a gate electrode 38 is formed in the P-well 32. Another NMOS transistor Tr2 consisting of the n.sup.+ -type source region 36, n.sup.+ -type drain region 39 and a gate electrode 40 is formed in the P-well 32. Similarly, formed is an NMOS transistor Tr3 comprising a source region (not numbered), a drain region 37, and a word line 41 acting as a gate. Also formed is an NMOS transistor Tr4 comprising a source region (not numbered), a drain region 39, and a word line 41 acting as a gate.
On the other hand, a PMOS transistor Tr5 comprising a p.sup.+ -type source region 42, a p.sup.+ -type drain region 43 and a gate electrode 37 is formed in the the N-well 33. Similarly, a PMOS transistor Tr6 comprising the p.sup.+ -type source region 42, a p.sup.+ -type drain region 44 and a gate electrode 40 is also formed within the element region inside the N-well 33. An interlayer dielectric film 45 is formed on the substrate 31 including the P-well 32 and the N-well 33. A contact hole 46 is formed through the interlayer dielectric film 45 to expose the n.sup.+ -type source region 36 in the P-well 32. The contact hole 46 is then filled with a conductive material for the connection between the source region 36 and a GND line 47. Another contact hole 48 is formed through the interlayer dielectric film 45 to expose the p.sup.+ -type source region 42 in the N-well 33. The contact hole 48 is then filled with a conductive material for the connection between the source region 42 and a Vcc line 49.
In the conventional six transistor type SRAM described above, a memory cell cross coupling wiring portion, the Vcc line 49, and the GND line 47 are formed using the same metal layer. In each memory cell, the GND line 47 is connected via the contact electrode 46 to only the n.sup.+ -type source region 36 in the P-well 32. Also, a P-well contact 14' serving to connect the P-well to the GND line is arranged outside the region where memory cell arrays are formed, as shown in FIG. 15. It is seen that FIG. 15 covers a case of 8-bit memory cell array. A GND line 53, which is common to the 8-bit memory cell array 52, is formed outside a region of 8-bit memory cell arrays. Also, the n.sup.+ -type source region 36 inside the P-well 32 is connected to the common GND line 53 via a GND lead line 54 which is directly connected to the n.sup.+ -type source region 36 for each memory cell. The P-well contact 14' and a GND contact 63' are formed adjacent to each other at the junction between the common GND line 53 and the lead line for each memory cell 52. It should be noted that the common GND line, GND lead line, and a local interconnector for each memory cell are formed of the same metal wire.
Where a P-well contact is formed in each memory cell in a 6-transistor type SRAM in an attempt to improve the latch-up resistance, it is difficult to make a layout such that the GND line does not go cross the memory cross coupling wiring. To avoid the difficulty, it is necessary to form a P-well contact outside a region where a memory transistor is formed. It is also necessary to place the PMOS and NMOS transistors within a memory cell apart from each other, resulting in a relatively large cell area.
Conventional techniques relevant to the present invention include, for example:
1. M. Helm, et al., 1993 Symp. on VLSI Tech. Digest of Technical Papers (1993), p. 65, "A LOW COST, MICROPROCESSOR COMPATIBLE, 18.4 .mu.m.sup.2, 6-T BULK CELL TECHNOLOGY FOR HIGH SPEED SRAMS", and PA1 2. T. Izawa, et al., IEDM Tech. Dig., pp 34.8.1-34.8.3, 1994. PA1 each memory cell has a P-well contact positioned adjacent to a GND contact and a Vcc contact, these contacts being commonly used for pull-down NMOS transistors and pull-up PMOS transistors, respectively, and placed between a pair of gates formed in parallel with a bit line; and PA1 the P-well contact consists of a p.sup.+ -type diffusion layer formed in the P-well in contact with an n.sup.+ -type source region of the pull-downMOS transistor, said p.sup.+ -type diffusion layer being positioned closer to the boundary between the P-well and the N-well than the source region.
An object of the present invention is to provide a semiconductor memory device which can be operated with a high stability and with a smaller power consumption and which permits diminishing the cell area, compared with the conventional 6-transistor type SRAM.